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論理回路シミュレーションによるCMOS符号誤り率測定回路の基本検討
https://metro-cit.repo.nii.ac.jp/records/151
https://metro-cit.repo.nii.ac.jp/records/1519830848a-a026-4284-8053-a3cfee5df61c
名前 / ファイル | ライセンス | アクション |
---|---|---|
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Item type | 紀要論文(ELS) / Departmental Bulletin Paper(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2013-03-01 | |||||
タイトル | ||||||
タイトル | 論理回路シミュレーションによるCMOS符号誤り率測定回路の基本検討 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Basic Examination for CMOS Bit Error Rate Detection Circuits though the Logical Circuit Simulations | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
言語 | en | |||||
主題 | PRBS | |||||
キーワード | ||||||
言語 | en | |||||
主題 | Synchronization | |||||
キーワード | ||||||
言語 | en | |||||
主題 | Error count | |||||
キーワード | ||||||
言語 | en | |||||
主題 | Out-synchronization | |||||
キーワード | ||||||
言語 | en | |||||
主題 | CMOS | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
ページ属性 | ||||||
内容記述タイプ | Other | |||||
内容記述 | P(論文) | |||||
著者名(日) |
大川, 典男
× 大川, 典男× 大島, 慶太× 芹澤, 和明 |
|||||
著者名よみ |
オオカワ, ノリオ
× オオカワ, ノリオ× オオシマ, ケイタ× セリザワ, カズアキ |
|||||
著者名(英) |
Ohkawa, Norio
× Ohkawa, Norio× Ooshima, Keita× Serizawa, Kazuaki |
|||||
著者所属(日) | ||||||
東京都立産業技術高等専門学校ものづくり工学科電子情報工学コース | ||||||
著者所属(日) | ||||||
東京都立産業技術高等専門学校 | ||||||
著者所属(日) | ||||||
東京都立産業技術高等専門学校 | ||||||
抄録(英) | ||||||
内容記述タイプ | Other | |||||
内容記述 | Bit error rate detection (ED) circuits which are installed in the receiver side, are employed to evaluate transmissionproperties of the optical communication systems. Although very expensive, these measuring circuits have been usedcompound semiconductor devices as GaAsMESFETs to get high-speed operation. This time, the examination circuitsof the ED circuits are applied to economic CMOSFETs, which have lower power consumption and expected to havehigh-speed operation by shortening those channel length. The basic functions of the ED circuits which includesynchronization, error counting, and monitoring control of out-synchronization are investigated through the logicalcircuit simulations on PSPICE. The operations of the ED circuits employed CMOSFETs are confirmed through thelogical circuit simulations. | |||||
雑誌書誌ID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA12210629 | |||||
書誌情報 |
東京都立産業技術高等専門学校研究紀要 en : Research reports of Tokyo Metropolitan College of Industrial Technology 巻 7, p. 77-81, 発行日 2013-03 |