@article{oai:metro-cit.repo.nii.ac.jp:00000151,
 author = {大川, 典男 and Ohkawa, Norio and 大島, 慶太 and Ooshima, Keita and 芹澤, 和明 and Serizawa, Kazuaki},
 journal = {東京都立産業技術高等専門学校研究紀要, Research reports of Tokyo Metropolitan College of Industrial Technology},
 month = {Mar},
 note = {P(論文), Bit error rate detection (ED) circuits which are installed in the receiver side, are employed to evaluate transmissionproperties of the optical communication systems. Although very expensive, these measuring circuits have been usedcompound semiconductor devices as GaAsMESFETs to get high-speed operation. This time, the examination circuitsof the ED circuits are applied to economic CMOSFETs, which have lower power consumption and expected to havehigh-speed operation by shortening those channel length. The basic functions of the ED circuits which includesynchronization, error counting, and monitoring control of out-synchronization are investigated through the logicalcircuit simulations on PSPICE. The operations of the ED circuits employed CMOSFETs are confirmed through thelogical circuit simulations.},
 pages = {77--81},
 title = {論理回路シミュレーションによるCMOS符号誤り率測定回路の基本検討},
 volume = {7},
 year = {2013},
 yomi = {オオカワ, ノリオ and オオシマ, ケイタ and セリザワ, カズアキ}
}